Responsibilities of the candidate:

• Depending on the expertise, the below set of responsibilities can be interpreted for fastspice(Primesim/Finesim) or Verilog (Xcelium/VCS) based verification.
• Guide and set the direction for the verification effort within your areas of expertise in any project that the team undertakes.
• Provide verification support to design projects by simulating, analyzing and debugging pre-silicon full chip designs.
• Develop Test cases/Stimulus to increase the functional coverage for all DRAM and emerging memory architectures and features.
• Participate in developing verification methodology and verification environments for advanced DRAM and emerging memory products.
• Co-work with international colleagues on developing new verification flows to take on the challenges in DRAM and emerging memory design.
• Develop and maintain test benches and test vectors using simulation tools and run regressions for coverage analysis and improvements.

Requirements:

• Exposure to Gate Level Simulations (Not unit/zero delay)
• Timing Checks & Analysis – Setup/Hold etc.
• Logic schematic analysis