Aprisa offers complete functionality for top-level hierarchical design and block-level implementation for sophisticated digital IC designs

The detail-route-centric architecture and hierarchical database enable fast design closure and optimal quality of results at a driven runtime.

We make real what matters!

This is your role

We are working on the next generation RTL-to-GDSII solution. You will be working primarily on C++ and should be able to completely own and drive the design and development of various pieces of the RTL synthesis technology, logic optimizations and power synthesis.

We are not looking for superheroes, just super minds!

Job Qualifications:

• Do you hold B.Tech or M.Tech in Computer Science (CSE), Electrical Engineering (EE), or Electronics and Communication Engineering (ECE) from a reputed engineering college?
• We are looking for someone who holds 2-8 years of dynamic experience in software development.
• Proficient in C/C++ and Strong knowledge and hands-on experience in designing and implementing efficient algorithms and data structures.
• Validated ability in creative and effective problem-solving. Exceptional analytical skills to analyze sophisticated systems and propose solutions.
• Should be able to guide and lead others, towards project completion.

Desirable Skills:

• Experience in RTL synthesis tool development will be a plus
• Proficient in SystemVerilog and VHDL, with expertise in UPF (Unified Power Format), DFT (Design for Testability), formal verification, and dynamic power analysis
• Skilled in RTL (Register-Transfer Level) and gate-level logic optimizations, adept at enhancing digital designs for improved performance and efficiency.
• Experienced in designing and implementing parallel algorithms, proficient in optimizing tasks for parallel execution to enhance performance.
• Proficient in scripting languages such as Python, Tcl, and Perl