What You’ll Learn

• Project Overview: The intern will work on Enhancing Chip Design and EDA Flow using RAG & LLM
• Skills You’ll Learn:
  • Using RAG (Retrieval Augmented Generation) with LLM (Large Language Model) 
  • Benchmark Speedup comparison with Gen AI versus traditional implementation

What You’ll Do

Intern will work with design team members and enhance automation of Chip Design and EDA using Gen AI (RAG & LLM) 

Location: Onsite at our San Jose office/headquarters 5 days a week 

• Work on enhancing execution of AI chip implementation
• Support your team, empowering their achievements, facilitating self-management, developing growth opportunities, and proactively planning for the future.
• Complete other responsibilities as assigned.

What You Bring

• Bachelors, Masters, or PhD in CS / EE
• GPA above 3.5
• RISC-V or ARM architecture knowledge
• Skilled at Python, RAG , Familiar with LLM’s
• You’re inclusive, adapting your style to the situation and diverse global norms of our people.
• An avid learner, you approach challenges with curiosity and resilience, seeking data to help build understanding.
• You’re collaborative, building relationships, humbly offering support and openly welcoming approaches.
• Innovative and creative, you proactively explore new ideas and adapt quickly to change.