Responsibilities

Looking for a Front-end Design team ASIC Engineer.

Architectural work: in-depth understanding of the architecture, and identification of problems and solutions.

All aspects of implementation: specification, design, verification, timing-closure, power-optimization, and flow automation.

Physical design work: timing path analysis, optimization of the logic for low power and area; highlighting issues and standard methodologies for power and area optimization.

Document and improve standard methodologies to make product successful.

Who You Are

Worked in architecture and definition of high-scale, high-performance ASICs.

Validated experience in implementation: specification, design, verification, formal verification, system testing.

Validated experience in physical design aspects: timing analysis and closure, power/area optimizations, macro size/placement analysis.

Validated experience in high bandwidth memory subsystems and timing closure.

Validated experience in flow automation (scripting, Makefiles, etc), and establishing guidelines for the team.

Good interpersonal skills, and validated leadership to accurately describe issues/improvements and lead team for on-time completion.

5+ years of hands on experience in large-scale, high-performance ASIC.

BS/MS in EE/CS.

Minimum Qualifications

End-to-end design experience from Verilog to gates, block planning, area/timing closure is helpful.

RTL development and verification (VCS, System Verilog, UVM/OVM, Formal verification)

Experienced in system debug and SW/HW bringup, system validation of silicon towards FCS.

Gate-level understanding of RTL and Synthesis

Programming/scripting skills (C, C++, Perl)

Hardware Emulation Platforms and tools (such as EVE, Veloce)

5+ years of substantial experience

Good written/verbal interpersonal skills and leadership skills.